1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for implementing high-speed operation of a delay locked loop that generates an output signal synchronized with an input signal.
2. Description of the Related Art
In widely used dual data synchronous dynamic random access memories (DDR SDRAMs) and Rambus DRAMs (RDRAMs), data is input to, or output from, a memory cell in synchronization with clock signals. The clock signals are input at a pin on the device and distributed to the entire device. A clock signal that arrives at a portion of the device that is a relatively long distance away from the input pin can be significantly delayed, as compared with a clock signal that arrives at a portion adjacent to the input pin. This delay makes it difficult to maintain synchronization between each portion of a DDR SDRAM or RDRAM. Thus, delay locked loops or phase locked loops are utilized to match the synchronization of clock signals. For example, delay locked loops are used to generate internal clock signals for performing data sampling at a valid data window for accurate data reception. Delay locked loops are further used to generate internal clock signals for synchronizing the edge of data to be transmitted with the edge of an external clock signal sent to a memory controller for ideal data transmission.
FIG. 1 is a block diagram showing a semiconductor memory device having a conventional delay locked loop. Referring to FIG. 1, in order to receive external clock signals CLK and CLKB and then generate internal clock signals ICLK synchronized with the received signals, a semiconductor memory device 100 includes input clock buffers 110 and 120, a delay locked loop (DLL) 140, output buffers 160 and 180. A first input clock buffer 110 receives the external clock signals CLK and CLKB to generate a reference clock signal REF, and a second input clock buffer 120 receives the external clock signal CLK and a feedback clock signal FDCLK to generate a feedback reference clock signal (FDREF). The DLL 140 compares the phase of the reference clock signal REF with the phase of the feedback reference clock signal FDREF and then delays the feedback reference clock signal FDREF by a predetermined time period depending on the comparison result. Then, the internal clock signals ICLK and ICLKB synchronized with the referenced clock signal REF are generated. Thus, the internal clock signal ICLK is set to lock the phase of the external clock signal CLK with the phase of the output data.
Thereafter, the internal clock signal ICLK is used as an actual clock signal for data reception and data transmission, as described above. For example, a first output buffer 160 transmits internal data DBi_F and DBi_S to an output pad DQ in response to the internal clock signal ICLK. Then, a second output buffer 180 having the same configuration as the first output buffer 160 is provided to generate the feedback clock signal FDCLK which delays the internal clock signal ICLK by;a predetermined time period. The feedback clock signal FDCLK is input to the second input clock buffer 120 together with the external clock signal CLK. The second input clock buffer 120 is comprised of a differential input buffer, as shown in FIG. 2. The differential input buffer serves to quickly sense a voltage difference between received two input signals to generate the result as an output signal, and it is primarily used in a semiconductor memory device which requires high speed operation.
However, the second input clock buffer 120 of FIG. 2 is limited in that it cannot perform a high speed operation which is characteristic of the differential input buffer. Since the two input signals, i.e., the external clock signal CLK and the feedback clock signal FDCLK are input to a differential input buffer with a delayed phase difference, a delay in sensing the voltage difference may occur compared to a complementary pair of input signals. This delay of the differential input buffer raises a problem in that the differential input buffer intended for a high-speed operation cannot perform its function properly. Furthermore, the delay is also reflected in phase locking, which is one of the primary operations of the DLL 140, thus preventing a high-speed operation of the DLL 140.
To solve the above problems, it is an objective of the present invention to provide a semiconductor memory device having a delay locked loop (DLL) which stably generates an output signal synchronized with an input signal at high speed.
Accordingly, to achieve the above objective, the present invention provides a semiconductor memory device for generating internal clock signals synchronized with external clock signals, which includes a first input clock buffer for receiving a pair of external clock signals to generate a reference clock signal, a DLL for receiving the reference clock signal and a feedback reference clock signal and phase-comparing those signals to generate a pair of internal clock signals, a first feedback clock buffer for receiving the pair of internal clock signals to generate a first feedback clock signal, a second feedback clock buffer for receiving the pair of internal clock signals to generate a second feedback clock signal, and a second input clock buffer for receiving the first and second feedback clock signals to generate the feedback reference clock signal.
Preferably, the first and second feedback clock signals are complementary. The first input clock buffer is a differential input buffer for sense amplifying a voltage level difference between the pair of external clock signals and generating the reference clock signal, while the second input clock buffer is a differential input buffer for sense amplifying a voltage level difference between the first and second feedback clock signals and generating the feedback reference clock signal. The first feedback clock buffer receives the pair of internal clock signals and generates the first feedback clock signal having the same phase as the internal clock signal, while the second feedback clock buffer receives the pair of internal clock signals and generates the second feedback clock signal having opposite phase to the internal clock signal.
The present invention employs an input clock buffer which receives complementary feedback clock signals to implement a high-speed operation of a DLL for generating internal clock signals which are synchronized with external clock signals. Accordingly, the present invention facilitates a high-speed operation of the input clock buffer, which is realized as a differential input buffer, and a DLL.